I will create a digital system design and perform rtl verification in systemverilog

Are you looking for a reliable engineer to design, verify, or debug your digital systems? You've found the right person.

I am a Computer Engineering graduate, with hands-on experience in RTL design, functional verification, and formal verification using industry-standard tools.

What I offer:

Functional Verification

• Testbench development using SystemVerilog
• Interface, clocking block, and fork-join based verification
• Coverage-driven verification: block, expression, toggle, and covergroups
• Simulation using Cadence Xcelium and Questa

RTL / FPGA Design

• HDL design and implementation on Basys 3, Spartan 3A
• DSP and signal processing on FPGA (audio processing, XADC, PWM)
• I2C, SPI, and other communication protocol integration

Why work with me?

• Graduate-level expertise in verification methodology
• Real project experience finding design bugs in protocol-compliant modules
• Clear communication and timely delivery
• Background in technical support means I understand client needs precisely

Message me before placing an order so I can confirm I'm the right fit for your project.