I will design fpga rtl in verilog or vhdl using vivado
FPGA Design Engineer, Verilog VHDL, Embedded Systems, Power Electronics
About this Gig
Need reliable FPGA RTL design, simulation, or debugging for your project?
I am an Electronics Engineer with 10+ years of experience in FPGA, digital logic, and embedded-system development. I help engineering teams, startups, and researchers turn specifications and block diagrams into clean, synthesizable, and well-documented HDL designs.
What I can help you with:
- FPGA RTL design using Verilog or VHDL
- Testbench development and functional simulation
- FSMs, FIFOs, arithmetic units, and pipelined datapaths
- UART, SPI, I2C, AXI, and other digital interfaces
- FPGA-based DSP, FIR/IIR filters, and fixed-point design
- IP integration and module interconnection
- Timing constraints, synthesis issues, and RTL debugging
- Vivado, Quartus, and ModelSim workflows
Depending on your package, you will receive:
- Clean and commented source code
- Synthesizable RTL design
- Self-checking testbench
- Simulation waveforms and results
- Design documentation or block diagram
- Clear explanation of the implementation
Each FPGA project has different requirements. Please message me before ordering with your device or board, software version, specifications, required interfaces, and expected deliverables.
My Portfolio
FAQ
❓Q1: What do you need to start?
A: Just message me your specs, block diagram, or the module you need. I'll confirm scope before you order.
❓Q2: Do you provide simulation results?
A: Yes, waveforms and a self-checking testbench are included.
❓Q3: Verilog or VHDL?
A: Both. Tell me your preference.
❓Q4: Which tools do you use?
A: Vivado, Quartus, and ModelSim; I can target Xilinx or Intel/Altera FPGAs.
❓Q5: Do you fix or debug existing HDL?
A: Yes, send me the files first.
Q6: Can you implement an IEEE paper?
A: Yes, I can implement and explain it. Note: I provide implementation and tutoring, not paper-writing for submission.

