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I will do fpga design and simulation in verilog and vhdl using vivado
FPGA Design Engineer, Verilog VHDL, Embedded Systems, Power Electronics
Electronics Engineer with 10+ years of experience in FPGA design, embedded systems, and power electronics. Skilled in Verilog, VHDL, MATLAB, Vivado, Quartus, DSP, and control systems. I help companies...
About this Gig
Looking for clean, reliable FPGA and RTL design that works the first time?
I'm an Electronics Engineer with 10+ years of hands-on experience in FPGA and digital design. I help startups, R&D teams, researchers, and students turn requirements and block diagrams into working, well-documented HDL.
What I can do for you:
- RTL design in Verilog and VHDL
- Testbenches, simulation, and verification (Vivado, Quartus, ModelSim)
- Digital logic: FSMs, FIFOs, arithmetic blocks, protocols (UART, SPI, I2C)
- DSP on FPGA: FIR/IIR filters, pipelined datapaths, fixed-point design
- IP integration, timing/constraint fixes, and debugging existing code
What you get: clean, commented, synthesizable code, simulation waveforms, and clear documentation so you understand exactly how it works.
Every project is custom please message me with your requirements before ordering so I can confirm scope, timeline, and the right package.
My Portfolio
FAQ
❓Q1: What do you need to start?
A: Just message me your specs, block diagram, or the module you need. I'll confirm scope before you order.
❓Q2: Do you provide simulation results?
A: Yes, waveforms and a self-checking testbench are included.
❓Q3: Verilog or VHDL?
A: Both. Tell me your preference.
❓Q4: Which tools do you use?
A: Vivado, Quartus, and ModelSim; I can target Xilinx or Intel/Altera FPGAs.
❓Q5: Do you fix or debug existing HDL?
A: Yes, send me the files first.
Q6: Can you implement an IEEE paper?
A: Yes, I can implement and explain it. Note: I provide implementation and tutoring, not paper-writing for submission.
