I will do uvm simulation using systemverilog for complex hdl module or soc design

Ahmed Egnr

Pakistan

I speak English

Embedded Systems Expert

Embedded Hardware/Firmware Design Professional having development work history targeting FPGA’s and Microcontrollers. Project lead designer , with focus on implementing DSP functions and uC/OS-ll on S...
Read More
About this Gig

UVM Simulation framework using System verilog for functional and RTL verification of your RTL design. DUT can be in any HDL language VHDL, Verilog or SV.

do uvm simulation using systemverilog for complex hdl module or soc design
Full Screen
do uvm simulation using systemverilog for complex hdl module or soc design

Platform:

FPGA

Sensors:

Temperature

•

Accelerometer

•

Ultrasonic

•

Microphone

•

Infrared

+5 more

Expertise:

Firmware development

•

RTOS

•

Debugging

•

SoC optimization

+5 more

My Portfolio

Related tags