I'm an Electronic Engineering graduate specialising in FPGA design from RTL concept to final bitstream. I design in Verilog and SystemVerilog, run functional verification, and implement full designs using Vivado, Vitis, and SDK toolchains.
My services cover digital design blocks, SoC integration, and AI/ML deployment on edge devices. Every deliverable is clean, well-documented, and built to last with clear communication and on-time delivery at every step.
Expertise on SoC Design, ASIC IP ,RISC-V and AI Accelerator I work smoothly with clients worldwide, regardless of timezone or background.... Read more