I will deploy your simulink model to zynq fpga using hdl coder and soc blockset

Pakistan

I speak Urdu, English, French

2 orders completed

FPGA Engineer Verilog VHDL RTL Vivado Quartus SoC

FPGA and Electronics engineer with 4+ years of experience in Verilog, VHDL, and RTL design on Xilinx Vivado and Intel Quartus. I specialize in Zynq SoC hardware-software co-design using MATLAB/Simulin...

About this Gig

Do you have a Simulink model but can't get it running on FPGA hardware? That gap is exactly what I solve.

I specialize in MATLAB/Simulink Xilinx Zynq SoC deployment using HDL Coder, Embedded Coder, SoC Blockset, and SoC Builder a rare skill most FPGA engineers don't have.

️What I Do:

HDL Coder IP core generation from Simulink subsystems.
SoC Blockset PS PL hardware-software partitioning
AXI4-Lite / AXI4-Stream interface mapping Fixed-point conversion and quantization Embedded Coder C/C++ for Zynq ARM Cortex-A9
ELF deployment on embedded Linux.
LabVIEW / MATLAB / UDP host interface design

Every Delivery Includes:

Simulink model with HDL Coder correctly configured
Synthesis-ready Verilog/VHDL source files
Vivado project with bitstream generated
ELF for ARM processor if PS-side code is needed
Deployment notes so you can rebuild independently

Why Choose Me:

Most FPGA engineers only write HDL. I work directly inside your Simulink environment no rework, no translation layer. Hands-on experience with Zynq and Zynq Ultrascale, AXI PS-PL communication, multi-threaded embedded Linux, and LabVIEW UDP interfaces.

Message me before ordering I'll confirm feasibility first.