I will write verilog, systemverilog, or vhdl modules and testbenches for fpga

Bora EE

Netherlands

I speak Turkish, English, French

Electrical Engineering services by a TUe MSc student specializing in RF, FPGA,

I offer: • Python/MATLAB signal processing scripts — filters, FFT, spectral analysis, data pipelines • Verilog/VHDL modules & testbenches — RTL design, verification, bug fixes • PCB & schematic review...
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About this Gig

Need Verilog, SystemVerilog, or VHDL for your FPGA project? I design clean, synthesizable RTL with proper verification.


What I deliver:

Combinational & sequential logic

FSMs and controllers

Communication interfaces (SPI, I2C, UART, AXI-Lite)

DSP blocks (filters, arithmetic, pipelines)

Memory controllers and FIFOs

Testbenches (SV or cocotb)

Bug fixing and code reviews


My approach:

Every module comes with a testbench. I verify functionality before delivery and provide waveforms showing correct operation. Code is lint-clean and follows industry conventions.


Background:

EE student at TU Eindhoven with FPGA coursework and hands-on project experience in digital design.


Targets:

Xilinx (Vivado), Intel/Altera (Quartus), Lattice, or vendor-agnostic code.


Message me with your requirements I'll confirm scope and timeline before you order.

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write verilog, systemverilog, or vhdl modules and testbenches for fpga
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write verilog, systemverilog, or vhdl modules and testbenches for fpga

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