Looks Like This Service Is On Hold

I will design and verify digital logic systems using verilog, system verilog, uvm

Medhavi

India

I speak English, Hindi

Passionate about Functional Verification, ASIC and Digital circuits!

Hi! This is Medhavi. I hold a master's degree in VLSI and Embedded System Engineering with a professional work experience of 3 years in MNC. Expertise: VIPs | Coverage | Regression Hardware Languages...
Read More
About this Gig

Brief about me: I am a Functional Verification professional with 6 months of in-depth and rigorous training in architecting complex verification environments using System Verilog and UVM frameworks.

Proficient in developing test plans, BFMs/UVCs for industry-standard protocols. Key achievements include implementing functional coverage and writing complex tests for coverage closure using regression and coverage analysis along with RTL debug.


Key offerings:

  • Design, develop and verify digital systems using Verilog | VHDL | System Verilog | UVM hardware descriptive language.
  • Write efficient and synthesizable code for FPGA and ASIC implementations.
  • Do university projects and assignments with running source code and test simulation results
  • Analyze and debug simulation results to identify and fix design issues.
  • Collaborate with cross-functional teams to integrate designed modules into larger systems.
  • Develop and maintain technical documentation for designed modules.


Standards/Protocols: AXI | AHB | APB | UART | SPI | I2C | CAN | PCIe | USB | Ethernet


Hardware Languages: Verilog | VHDL | System Verilog | UVM


Software Languages: C | C++ | Python


Simulators: VCS | Questa | ModelSim

Read More
design and verify digital logic systems using verilog, system verilog, uvm
Full Screen
design and verify digital logic systems using verilog, system verilog, uvm
Full Screen
Full Screen
design and verify digital logic systems using verilog, system verilog, uvmdesign and verify digital logic systems using verilog, system verilog, uvmdesign and verify digital logic systems using verilog, system verilog, uvm

My Portfolio

Related tags