d
denyrand

denny

@denyrand

Engineer

Pakistan
English
About me
I have strong expertise in digital design verification using UVM, Verilog, and SystemVerilog. I specialize in building robust testbenches, developing functional coverage, and debugging complex RTL designs. I have hands-on experience with industry-standard tools such as Cadence verification environments and Xilinx Vivado. My background in digital logic design enables me to deliver reliable, efficient, and high-quality verification solutions. I help clients ensure first-time-right silicon through thorough and scalable verification methodologies.... Read more

Skills

d
denyrand
denny
Offline • 
Average response time: 1 hour

See my services

Programming & Tech
I will design solar wind hybrid systems in system advisor model sam
From$10 / projectMore details
Programming & Tech
I will do digital logic design, verilog, systemverilog, uvm, and fpga design
From$5 / projectMore details

Work experience

Employee of the Year

SemiEdge • Part-time

Jan 2020 - Present • 6 yrs 4 mos

FPGA Desgn Engineer at SemiEdge