e
esha_sci

Esha

@esha_sci

FPGA, Verilog, MATLAB and Python Engineer

South Korea
English, Urdu
About me
I am an engineering researcher and developer specializing in FPGA design, Verilog/SystemVerilog, MATLAB, Python, and engineering simulations. I work with RTL design, testbenches, functional simulation, debugging, FPGA synthesis, and Xilinx Vivado. I also develop MATLAB and Python solutions for signal processing, wireless communications, data analysis, machine learning, and scientific visualization. I provide technical research support including proofreading, formatting, figures, tables, and result visualization, with a focus on clear code and professional work.... Read more

Skills

e
esha_sci
Esha
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See my services

Embedded Systems & IoT
I will design, simulate and debug verilog fpga rtl modules