I will rtl design and verification riscv systemverilog fpga
About this Gig
I design, build, and verify digital hardware from individual RTL modules to complete processor architectures.
️ What I offer:
- Custom RTL design in Verilog / SystemVerilog
- RISC-V processor design single-cycle, multi-cycle, pipelined, or custom extensions
- UVM-based verification layered testbenches, scoreboards, functional coverage
- Testbench development & functional verification
- FPGA implementation & prototyping (Xilinx Vivado, Nexys A7)
- Memory system design caches, FIFOs, clock-domain crossing
- Communication protocol controllers UART, SPI, I2C
- PCB design (KiCad)
My process:
Every design I deliver is simulated, verified against edge cases, and documented clearly not just functional, but understandable. Whether you need a quick module, a full verification testbench, or a complete processor built from scratch, I bring the same rigor to every project.
Before ordering, message me with your requirements (spec, target tool/FPGA board, deadline) so I can confirm scope and timeline.
Let's build something solid.
Platform:
FPGA
My Portfolio
Other Electronics Engineering Services I Offer
FAQ
Q: Do you provide the source code and testbenches?
Yes - all deliverables include commented source files and testbenches used for verification.
Q: Can you work with an existing codebase I already have?
Yes, share your files in the requirements step and I'll review scope before starting.
Q: Do you support formal verification / UVM?
Yes - I build layered UVM testbenches (drivers, monitors, scoreboards, sequences) for structured, reusable verification, not just directed testbenches.

