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hamzanisar1997

Hamza N

@hamzanisar1997

Senior RTL Design Engineer

Malaysia
English, Urdu
About me
I am a Senior RTL Design Engineer with over 6 years of experience in ASIC and FPGA development. I specialize in RTL design, IP integration, and FPGA prototyping using Verilog and SystemVerilog. I have a proven track record of delivering complex AI and networking SoC designs while leading teams through RTL sign-off and timing closure on advanced nodes.... Read more

Skills

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hamzanisar1997
Hamza N
Offline • 
Average response time: 1 hour

See my services

Embedded Systems & IoT
I will do verilog vhdl implementation on fpga soc
From$5 / projectMore details

Work experience

Dream_Controller

Senior ASIC Engineer

Dream Controller • Freelance

Jul 2020 - Present • 6 yrs

Contributing to RTL IP development, IP integration, RTL quality sign-off, and timing closure for next-generation Memory Systems SoCs on advanced TSMC nodes. Led end-to-end RTL IP static sign-off including Lint, CDC, RDC, and synthesis. Developed Fusion Compiler optimization flows that improved block WNS by 120ps and reduced TNS by 70% through script optimization.