I will help verifying complex design by developing sv, uvm testbench

Maniyar

India

I speak Gujarati, English, Hindi

2 orders completed

ASIC verification

I have hands-on experience in a wide range of digital design and verification projects using Verilog HDL. My expertise spans across Digital Electronics, Verilog HDL, System Verilog, UVM methodologies....
Read More
About this Gig

I can help to verify complex RTL designs with the help of SV,UVM based TB envioronment, which also covers functional/code coverage aspects (need basis)

help verifying complex design by developing sv, uvm testbench
Full Screen
help verifying complex design by developing sv, uvm testbench
Full Screen
Full Screen
help verifying complex design by developing sv, uvm testbenchhelp verifying complex design by developing sv, uvm testbenchhelp verifying complex design by developing sv, uvm testbench

Related tags