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I will develop fpga hls designs using c cpp and vitis hls
FPGA and AI Developer with 8 Years Experience in Verilog VHDL HLS
I'm an FPGA & Digital Hardware Engineer with 8+ years of hands-on experience in RTL design, debugging, verification, optimization, and hardware acceleration.
I work with Verilog, VHDL, SystemVerilog,...
Level 1
Has met certain performance criteria and shows strong potential in the marketplace.
About this Gig
Need to accelerate your C/C++ algorithm on an FPGA?
I will develop and optimize FPGA HLS designs using C/C++ and Vitis HLS, converting your algorithm into efficient, synthesizable hardware.
I can help with:
- C/C++ to FPGA HLS development
- Vitis HLS project creation
- HLS IP development
- C simulation & C/RTL co-simulation
- AXI interfaces and hardware integration
- Loop pipelining & unrolling
- Dataflow optimization
- Latency and resource optimization
- DSP and signal-processing algorithms
- Image/data-processing accelerators
- HLS debugging and synthesis issues
- Zynq/ZynqMP FPGA acceleration
My goal is not simply to make your HLS code synthesize. I focus on creating reliable, efficient hardware with a practical balance between performance, latency and FPGA resources.
Tools: Vitis HLS, Vivado, C/C++, Verilog/VHDL and FPGA development workflows.
Have an algorithm or existing C/C++ code you want to accelerate? Send me the details before ordering so I can recommend the right package.
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FAQ
Q1. What is HLS?
High-Level Synthesis (HLS) converts algorithms written in languages such as C/C++ into synthesizable hardware suitable for FPGA implementation.
Q2. Do you work with Vitis HLS?
Yes. I can develop, simulate, synthesize and optimize HLS designs using Vitis HLS.
Q3. Can you convert my existing C/C++ code to FPGA hardware?
Yes. I can analyze your existing C/C++ algorithm and adapt it for HLS while considering synthesizability, latency, throughput and FPGA resource usage.
Q4. Can you optimize an existing HLS design?
Yes. I can work on pipeline, loop unrolling, dataflow, memory access and interface optimization to improve performance and/or resource utilization.
Q5. Can you create AXI interfaces?
Yes. I can develop HLS IP using appropriate AXI-based interfaces depending on your system architecture and requirements.
Q6. Can you integrate the HLS IP into Vivado?
Yes. Integration into a Vivado FPGA project can be included depending on the package and project complexity.
Q7. Do you support Zynq and ZynqMP?
Yes. I can work with Zynq/ZynqMP-based FPGA acceleration workflows, including HLS IP and hardware integration.
Q8. Can you work with DSP or image-processing algorithms?
Yes. HLS is particularly useful for many DSP, signal-processing, image-processing and data-processing applications.
Q9. Will you provide the source code?
Yes. The agreed deliverables can include the C/C++ HLS source, Vitis HLS project and generated IP/RTL files as applicable.
Q10. Should I contact you before ordering?
For anything beyond a small standalone HLS module, yes. Send your algorithm, target FPGA, existing code and performance requirements so I can recommend the appropriate package.
