I will design a custom uart, spi, or i2c interface in verilog or systemverilog

Custom UART / SPI / I2C Interface Design in Verilog Simulation-Verified RTL

Need a reliable communication interface for your FPGA or digital design project? I design and verify protocol modules in Verilog/SystemVerilog built to work in real hardware, not just look right in a quick simulation.

Every module gets clean, commented RTL and a self-checking testbench with proof of correct operation before delivery. If your design spans multiple clock domains, I handle it properly with gray-code pointers and synchronizers, not a shortcut that causes problems later.

Recent work:

Configurable-baud UART with async FIFOs, verified via loopback and error-injection testing, zero timing violations on real FPGA hardware

AXI-integrated hardware accelerator, verified against an independent reference model

Full CPU/system design verified against an industry-standard test suite

I can share repos, waveforms, and verification results before you order, so you know exactly what you're getting.

Good fit for:

• Adding a UART/SPI/I2C interface to an FPGA design
• A standalone, reusable IP block
• Clock-domain-safe FIFO or bus work
• Testbench writing for your own RTL

Tools: Vivado, Quartus, ModelSim/Verilator, Py