I will write systemverilog, verilog testbenches and verify your rtl design

Hasnat S

Pakistan

I speak Urdu, English

RTL Design Verification Engineer

I am a digital design engineer with hands-on experience across full-custom RTL, verification, and FPGA integration. I specialize in architecture, self-checking testbenches, and timing closure for proj...
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About this Gig

Have RTL that needs real verification, not just a quick simulation check? I write self-checking testbenches and verification environments in Verilog/SystemVerilog built to catch bugs, not just confirm the happy path works.

How I work:

Testbenches compare against expected results automatically, not something you eyeball in a waveform viewer. For arithmetic or datapath-heavy modules, I cross-check against an independent reference model (typically Python) for real confidence the logic is correct.

Recent work:

CPU core verified against an industry-standard functional test suite (all opcodes, addressing modes, interrupts)

Hardware accelerator verified against a Python golden model 896/896 operations matched

Interface/protocol modules tested with loopback and deliberate error-injection

I can share repos and results before you order.

Good fit for:

  • RTL needing an independent testbench
  • Coverage/edge-case testing beyond basic tests
  • Verification sanity-check before synthesis/tapeout
  • Academic or personal projects needing real rigor

Tools: ModelSim/Questa, Verilator, Python, basic SVA/formal (SymbiYosys)

Unsure which package fits? Send your RTL and intended behavior first happy to scope it.

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write systemverilog, verilog testbenches and verify your rtl design
write systemverilog, verilog testbenches and verify your rtl design
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write systemverilog, verilog testbenches and verify your rtl designwrite systemverilog, verilog testbenches and verify your rtl designwrite systemverilog, verilog testbenches and verify your rtl designwrite systemverilog, verilog testbenches and verify your rtl designwrite systemverilog, verilog testbenches and verify your rtl design

Platform:

FPGA

Expertise:

Debugging

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SoC optimization

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Testing

•

AI

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Programming

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