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Jahnavi Bingi
@jahnavi_bingi
Verilog RTL, FPGA Design Engineer
India
English, Telugu, Hindi
About me
I am an Electronics and Communication Engineering student focused on Verilog RTL design, FPGA development, and digital system design.
I work with synthesizable Verilog HDL and have hands-on experience developing and verifying digital modules using tools such as Xilinx Vivado. My project experience includes DMA controllers, UART communication, priority queue architectures, and processor-related RTL design.
I can help with RTL module development, FSMs, FIFOs, UART, counters, registers, testbenches, simulation, debugging, and other digital design tasks.
Skills
Jahnavi Bingi
Offline •
Average response time: 1 hour
See my services
Embedded Systems & IoT
I will design synthesizable verilog rtl modules
