I'm a Professional FPGA Design Engineer specializing in RTL and HLS development using Verilog, VHDL, & SystemVerilog. Software I use includes Xilinx Vivado, Vitis, Vitis HLS, Vitis AI, Intel Quartus, and ModelSim. I design high-performance, low-latency FPGA systems for AI acceleration, edge computing, embedded systems, robotics, fintech, telecom, PCIe, AXI, UART, SPI, I2C, DDR & real-time image processing. Services include FPGA design, RTL coding, simulation, timing closure, IP integration, debugging, hardware acceleration, and full project documentation for reliable, industry-ready solutions.... Read more