
Mohamed Atheef
FPGA Design Engineer Verilog VHDL MATLAB DSP
Skills

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Work experience
Custom RISC-V CPU with DSP Accelerator on FPGA
AMD • Part-time
Feb 2026 - Present • 3 mos
Currently developing a custom RISC-V processor integrated with a DSP accelerator on FPGA. • Designing CPU architecture and instruction pipeline using Verilog • Integrating DSP modules for efficient signal processing • Performing simulation and verification using ModelSim/Vivado • Optimizing performance and hardware resource utilization This project enhances my expertise in FPGA systems, processor design, and hardware acceleration.
FPGA-Based Jamming Detection System
University of California • Full-time
Apr 2022 - Present • 4 yrs 1 mo
Designed and implemented a real-time jamming detection system on FPGA for secure communication applications. • Developed DSP algorithms for detecting interference under AWGN conditions • Implemented designs using Verilog and performed simulations • Analyzed signals using MATLAB (FFT and filtering techniques) • Evaluated system performance under different jamming scenarios This project strengthened my skills in FPGA design, DSP, and communication systems.