I will design and debug asic rtl using verilog and systemverilog

Mohamed H

Egypt

I speak English, Arabic

Electronics and Communications Engineer

I am an Electronics and Communications Engineer ranked 4th in my class with expertise in ASIC Physical Design and Digital IC Design. I have hands-on experience in RTL-to-GDSII implementation using Syn...
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About this Gig

I will design, debug, and verify Verilog/SystemVerilog RTL modules with testbenches and simulation analysis, delivering clean and synthesizable code based on your requirements.

design and debug asic rtl using verilog and systemverilog
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design and debug asic rtl using verilog and systemverilog

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