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Digital Logic Design,RISCV, Embedded Systems , FPGA Solutions, Technical Writer
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Design of RISCV CORE
Company • Self-employed
Feb 2026 - Jun 2026 • 4 mos
I have designed data path of 3 STAGE PIPELINE RISCV CORE and written system verilog modules separately of every part of Core and then i have written TOP LEVEL Module of the RISCV Core. Then i tested Core using System Verilog Testbench.