I will verify your digital IP using systemverilog and uvm

Daud

Pakistan

I speak English

Making digital design and verification easier

I am a Digital Design & Verification Engineer specializing in Verilog, SystemVerilog, UVM, and RTL design. I have hands-on experience in APB, AHB, AXI, RISC-V, UART, and SoC verification. I develop pr...
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About this Gig

Are you looking for an experienced Digital Verification Engineer to develop a robust, scalable, and reusable UVM (Universal Verification Methodology) testbench for your IP? I specialize in building complete verification environments from scratch to achieve 100% functional and code coverage.

What I Can Do For Your IP:

  • Architecture & Planning: Review your design specifications and create a comprehensive verification plan (vplan).
  • Testbench Development: Build complete UVM testbenches including factory overrides, configurations, environments, agents, drivers, sequencers, and monitors.
  • Scoreboards & Predictors: Implement data-integrity scoreboards and behavioral models to track transaction accuracy.
  • Assertions (SVA): Write SystemVerilog Assertions to catch protocol violations at the interface boundary.
  • Coverage Driven Verification (CDV): Design functional coverage groups (covergroups) and cross-coverage targets.
  • Debugging: Analyze waveforms (FSDB/VCD) using tools like Verdi or Questa to fix RTL bugs and constraint issues.

Protocols & Interfaces I Work With:

  • Bus Protocols: AMBA (AXI4, AXI-Lite, AHB, APB)
  • Serial Interfaces: UART, SPI, I2C, I3C
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verify your digital IP using systemverilog and uvm
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verify your digital IP using systemverilog and uvm
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verify your digital IP using systemverilog and uvmverify your digital IP using systemverilog and uvmverify your digital IP using systemverilog and uvm

Platform:

FPGA

Sensors:

Microphone

Expertise:

Debugging

•

SoC optimization

•

Testing

•

Programming

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