Muhammadans

@muhammadans643

Computer Engineer Digital Systems and FPGA Designer Machine Learning

Pakistan

English

About me

I’m a Computer Engineering graduate from UET with 4+ years of hands-on experience in Digital Logic Design, VLSI, ASIC, and FPGA development. I specialize in Verilog/VHDL and the complete Cadence RTL-to-GDSII flow, including RTL design, functional verification, synthesis, floorplanning, placement, CTS, routing, timing closure, and sign-off checks. I also work with MATLAB, C/C++, Python, and Machine Learning. I focus on delivering clean, optimized, and well-documented designs with clear communication, reliability, and on-time delivery.... Read more

Skills