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I will help with asic physical design and static timing analysis
I am an Electronics Engineering graduate
Hi, I'm Naeem Ul Hasan, passionate about digital and analog IC design. I offer services in Verilog RTL coding, digital logic design, FSM development, testbench creation, simulation, and analog CMOS ci...
About this Gig
Need help with ASIC Physical Design or VLSI backend analysis?
I provide support for physical design workflows, static timing analysis (STA), and ASIC implementation tasks based on your project requirements.
**My services include:**
- ASIC and VLSI physical design support
- Static timing analysis (STA)
- Setup and hold timing analysis
- Critical path and slack analysis
- Synthesis and timing report analysis
- Floorplanning and placement support
- Timing issue identification and troubleshooting
- Technical documentation and recommendations
**What you'll receive:**
Clear technical analysis
Identification of potential design issues
Practical improvement suggestions
Reports and documentation according to your package
Please share your project files, timing constraints, reports, and preferred tools before ordering. Contact me first for complex designs or implementation requirements so we can confirm feasibility, scope, pricing, and delivery time.
Let's improve your ASIC design workflow together!
FAQ
Q1. What is ASIC Physical Design?
ASIC Physical Design converts a synthesized netlist into a physical chip layout through stages such as floorplanning, placement, clock tree synthesis, routing, and verification.
Q2. What is Static Timing Analysis (STA)?
STA checks whether signal paths meet timing requirements without requiring simulation of every possible input sequence.
Q3. Can you analyze setup and hold violations?
Yes, I can review supplied timing reports, identify critical paths and reported violations, and recommend possible corrective actions within the agreed scope.
Q4. Which EDA tools do you support?
Tool support depends on the project and available environment. Please contact me before ordering to confirm compatibility with your preferred tools.
Q5. Do I need to provide design files?
Please provide relevant netlists, timing reports, SDC constraints, technology information, or other available project files, depending on the service selected.
Q6. Do you provide complete RTL-to-GDSII implementation?
Implementation scope depends on design complexity, tool availability, and required technology files. Please contact me first to confirm which stages can be delivered.
