I'm a VLSI Physical Design engineer (RTL-to-GDSII, Cadence Genus/Innovus) who also builds AI software, a rare combination. I interned at a semiconductor firm, closing timing with zero DRC/LVS violations on a 28nm PDK. I've taken an AI accelerator (systolic array) from RTL to GDSII on Sky130, and built LSTM/CNN accelerators achieving 150x power savings on FPGA. I also build RAG chatbots and AI agents using LangChain and Python. Precise, tested, documented work. Tell me which side of your problem you need, and I'll tell you honestly what's realistic before we start.... Read more