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suhas_997

Suhas B V

@suhas_997

VLSI Physical Design Engineer Trainee

India
English, Kannada
About me
My training in VLSI Physical Design has provided me hands-on exposure to implementing a 40nm SoC block. I was actively involved in the APR implementation stages, including placement optimization, Clock Tree Synthesis, detailed routing, and timing-driven optimization.... Read more

Skills

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suhas_997
Suhas B V
Offline • 

See my services

Programming & Tech
I will help in vlsi physical design, cmos and low power design
From$5 / projectMore details

Portfolio

Work experience

VLSI Physical Design Trainee

R V skills

Jul 2025 - Jan 2026 • 6 mos

Designed a low-power multi-voltage physical design block on 40nm technology node at 1 GHz, with 34 macros and ˜0.4M gates over 4.52 mm2 area, dual supplies (1.18V/1.1V) across 9 power domains,multi-Vt cells, 450 mW power budget, 5% IR drop, 7 metal layers, and low-power features including voltage islands, shutdown blocks, and clock gating