I will design custom rtl logic in verilog and system verilog

Ramish Hassan

Pakistan

I speak English, German

Hardware programmer

Hello! I am an engineer specializing in Digital IC Design, RTL architecture, and C/C++ systems programming. I have practical experience in front-end design, writing and verifying Verilog/System Verilo...
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About this Gig

Digital IC Design, RTL Coding & Verification

Need robust, synthesizable RTL and comprehensive verification? I specialize in efficient Verilog and SystemVerilog IP cores, custom datapaths, and verification environments.

What I Offer:

  • Custom RTL Design: Pipelined processors (e.g., RISC-V), arithmetic units, and complex datapaths.
  • Sequential & FSM Logic: Memory controllers, FIFOs, and Mealy/Moore state machines.
  • SoC Protocols: AMBA APB, AHB, and AXI master-slave interfaces.
  • Advanced Verification: Layered testbenches, SystemVerilog Assertions (SVA), and UVM.
  • FPGA Prototyping: QSF mapping and Platform Designer integration.

Tools & Hardware:

  • Languages: Verilog, SystemVerilog, C/C++
  • EDA Tools: ModelSim, Questa Sim, Quartus, Vivado
  • Targets: Intel Cyclone IV/V (DE1-SoC, DE10-Lite), Xilinx Zynq-7000

Why Choose Me? I provide strictly synthesizable, well-commented code backed by thorough corner-case verification to ensure flawless hardware implementation.

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design custom rtl logic in verilog and system verilog
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design custom rtl logic in verilog and system verilog

Platform:

FPGA

Sensors:

Other

Expertise:

Debugging

•

Microcontrollers

•

Testing

•

Programming

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