I will design and optimize ai accelerators for fpga and asic

Are you looking for a custom AI accelerator, systolic array, FPGA design, or ASIC-ready RTL solution?

I will design and optimize AI hardware accelerators using Verilog/SystemVerilog for FPGA and ASIC applications. Services include systolic array accelerators, MAC and processing-element design, matrix multiplication engines, CNN accelerators, INT4/INT8 datapaths, pipelining, zero-skipping, sparsity-aware architectures, and custom arithmetic units.

I can provide RTL design, simulation, verification, testbenches, waveform analysis, synthesis-ready code, block diagrams, and technical documentation.

Supported tools and flows include Cadence synthesis tools with a 45 nm PDK, Xilinx Vivado, Yosys, OpenLane, Verilator, Icarus Verilog, GTKWave, and open-source ASIC flows using SKY130.

Designs can be optimized for area, timing, power, throughput, latency, or FPGA resource usage. Deliverables may include source code, testbench, synthesis reports, timing and area analysis, netlists, and architecture diagrams.

Please contact me before ordering to discuss your model, precision, target FPGA or PDK, clock goal, and required deliverables.