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Tuna
@tianyixue
Computer Engineering Student
United States
English
About me
I am a Computer Engineering student at UC Santa Barbara with hands-on knowledge of RTL design, simulation, and verification for FPGA and ASIC applications. I have experience developing and testing digital logic using SystemVerilog, including finite-state machines, communication interfaces, arbitration logic, and data-processing modules. I am a rapid learner dedicated to building reliable, efficient hardware systems and expanding my expertise in digital design and computer architecture.
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Embedded Systems & IoT
I will design rtl, simulate rtl code, or use codex for design
