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I will design and verify fpga rtl modules in verilog or vhdl
About this Gig
I'm an FPGA design engineer with production experience in Verilog and VHDL
on Xilinx (Vivado/Vitis), Microchip (Libero, PolarFire) devices and Altera (Quartus).
WHAT YOU GET
- Synthesizable RTL: clean, commented, lint-clean code
- A self-checking testbench and simulation waveforms proving it works
- Synthesis and timing reports, not just a zip of source files
- A short design note explaining architecture, interfaces and assumptions
TYPICAL WORK
- AXI4 / AXI-Lite / AXI-Stream peripherals, bridges and DMA paths
- Image and video processing pipelines
- DSP blocks: filters, CIC, FFT front-ends
- DDR and high-speed interface integration
- Clock domain crossing and timing closure
TOOLCHAINS
Vivado, Vitis, Libero SoC, Quartus, ModelSim/QuestaSim, .
HOW IT RUNS
You get progress updates at agreed checkpoints and simulation evidence
before delivery, so there are no surprises at the end.
Not sure how to scope your project? Send me your spec, block diagram or
datasheet. I'll tell you honestly whether it's a fit, what it will cost
and how long it will take, before you order anything.
Platform:
FPGA
FAQ
Which FPGA vendors and families do you work with?
All three majors. AMD-Xilinx (Artix, Zynq, Kria) in Vivado/Vitis, Intel-Altera (Cyclone, Arria, MAX 10) in Quartus Prime, and Microchip PolarFire in Libero SoC. Targeting something else? Message me and I'll say honestly if it's a fit.
Can you work from just a block diagram or a datasheet?
Yes. Send whatever you have — spec, timing diagram, datasheet, or existing code. I'll come back with a written scope and a fixed price before you order.
Will I get the source code and the right to use it?
Yes. You receive full source, testbench and project files, with full commercial rights on delivery. No hidden licensing, no encrypted netlists.
Can you fix or extend existing RTL instead of writing new?
Yes, that's a common request — debugging, timing closure, or adding features to inherited code. Send the repo and describe the problem.
Do you provide hardware verification on a real board?
I verify in simulation as standard. On-board bring-up is possible if you have the target hardware and can share access or capture data
