I will verify your verilog or systemverilog rtl

Vasu A

India

I speak English

Design Verification Engineer

I am a Design Verification Engineer with extensive experience in SoC and IP-level verification using SystemVerilog and UVM. I specialize in AMBA protocols, functional coverage, and SVA assertions to e...
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About this Gig

I will verify your Verilog or SystemVerilog RTL

This targets students and startups.

Deliverables

  • Testbench
  • Directed tests
  • Random tests
  • Waveform debugging
  • Bug report
  • Functional verification

Good keywords

  • Verilog
  • RTL
  • FPGA
  • ASIC
  • Verification


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verify your verilog or systemverilog rtl
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verify your verilog or systemverilog rtl
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