I will write vhdl verilog rtl code with testbench and vivado simulation

Pakistan

I speak Urdu, English

FPGA Design VHDL Verilog MATLAB and Python

I design and verify digital hardware — RTL in VHDL and Verilog, with testbenches that prove the design actually works. My work covers combinational and sequential logic, finite state machines, UART/S...
About this Gig

I do RTL design and verification VHDL and Verilog, properly tested.


Most people can write code that compiles. I write code that's clean, synthesizable, and comes with a testbench that actually proves it works.


WHAT YOU GET

- Well-commented, synthesizable RTL (VHDL or Verilog your choice)

- A working testbench with real test cases

- Simulation waveform screenshots

- Source files you can open and run yourself


WHAT I BUILD

- Combinational & sequential logic: adders, ALUs, multipliers, comparators

- Finite state machines: controllers, sequence detectors, protocol handlers

- Counters, shift registers, register files, memory blocks

- UART / SPI / I2C controllers

- Datapaths, pipelines, processor cores (RISC-V)

- Testbenches and verification for code you already have


TOOLS

Vivado (primary), GHDL, ModelSim. Tell me yours and I'll match it.


RECENT WORK

A 5-stage pipelined RISC-V processor in VHDL with 1-bit, 2-bit and 3-bit branch predictors full forwarding, stall and flush logic, validated against a Python reference model.


Message me your spec before ordering. I'll tell you straight whether I can do it and which package fits.

Platform:

FPGA

Expertise:

Microcontrollers

Programming

Signal processing