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Zeerak
@zeerakulhassan
FPGA and RTL Design Engineer, Verilog VHDL SystemVerilog Vivado
Pakistan
English, Urdu, Hindi, Pashto
About me
FPGA & RTL Design Engineer | 4+ Yrs | Verilog, VHDL, SystemVerilog, Vivado
I design, verify and debug reliable digital systems for startups, researchers and engineers worldwide.
Services:
• FPGA Design (Vivado, Quartus, Vitis HLS)
• RTL Coding (Verilog, SystemVerilog, VHDL)
• Testbenches, UVM, ModelSim, QuestaSim
• SoC / Zynq / MicroBlaze, AXI, I2C, SPI, UART
• PetaLinux, TCL, Git, RFSoC, ADRV9001
• PCB (Altium, KiCad), MATLAB, DSP
Boards: Nexys A7, Basys 3, Zybo, ZedBoard, ZC706.
Hardware Engineer at SWARM, Riyadh. B.Sc. EE, IIUI.
Clean code, free consultation, on-time delivery.
Skills
Zeerak
Offline •
Average response time: 1 hour
See my services
Embedded Systems & IoT
I will do verilog vhdl systemverilog rtl coding for fpga on vivado quartus xilinx
Embedded Systems & IoT
I will debug fix and verify your verilog vhdl systemverilog fpga rtl design
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