I will do system verilog coding for fpga and asic

Hi there! Thanks for visiting my gig.

I will translate your design specification to RTL using HDL Verilog/System Verilog to program FPGAs or design ASIC. I can verify the functionality of your Verilog code, debug it, and can perform coverage analysis including:

• Code (Block, Expression, Toggle)
• FSM
• Functional

I can design the project with different protocols (e.g. SPI) and can design at any level for instance ALU, Adders, Multipliers, Algorithms, etc. My services include:

• Block Schematic
• RTL Design
• Verilog HDL/System Verilog
• Testbench
• Simulations
• Verification
• FPGA
• Logic Synthesis
• Physical Design including Layout
• Coverage Analysis
• SVA (System Verilog Assertions)
• Netlist Verification

Tools I use:

• Xilinx Vivado
• Xilinx ISE
• Incisive/Xcelium/VCS
• Modelsim
• Genus
• Innovus
• Virtuoso
• Openlane
• Iverilog

Note: You are kindly requested to contact me before placing the order if your project is complex, so that we may agree and lock design specifications before the order is placed.